ASUS Proprietary but Impressive OC Socket Examined – Is it even LGA 2011?

[Mini-Editorial] I was pretty impressed by ASUS’s recent innovation in the socket sector. I am talking ofcourse about the ASUS OC Socket, which boasts improved OC performance by granting the user more stability and higher voltage control thanks to more pins. Now while this all an impressive feat for an AIB to do, it begs the question whether we are looking at LGA 2011 at all.

Is the ASUS OC Socket Intel LGA 2011 at all? Or is it actually the ‘LGA 2017′ Homegrown Socket?

The LGA 2011-3 is Intel’s Socket designed to be used with its HEDT Processors. Now the 2011 indicates the amounts of pins in the socket and the ’3′ indicates the revision of the socket. Now that means that any LGA 2011 socket will have exactly 2011 pins. So is the ASUS OC Socket LGA 2011 then? Umm, no technically it is not. The ASUS OC Socket is compatible with the LGA 2011 but it is not in reality 2011. If you were to give it a name in Intel’s current nomenclature it would be LGA 2017 (the OC Socket has 6 additional pins apparently). Since ASUS has basically designed a completely new socket, I wouldn’t expect it to be rock solid and completely bug free at launch.

Let’s take a closer look at what exactly ASUS has accomplished. Haswell uses an FIVR (Fully Integrated Voltage Regulator) and as the new processor architectures have appeared, Intel has become more and more secretive about the workings of the pinouts. Not knowing where the voltage lines lay, ASUS basically bruteforced the entire contact points present on 2011 processors to figure out where the new pins should touch to grant unhindered access to voltage. The result? ASUS OC Socket lets you effectively bypass any FIVR compulsions Intel has in place. This means that you will be able to achieve higher and more stable overclocks probably at a lower voltage. I have a feeling ASUS might be a trend setter with this and seeing they already have a patent pending, might earn big bucks from it too.

And that’s not it either. We already know that Intel is dropping the FIVR, so it doesn’t come as a surprise that it is not that fine tuned because the extra pin outs on an ASUS Proprietary OC Socket allow access to voltage lines for DDR4 Voltage, enabling greater overclocking than you would normally be able to achieve. Now we didn’t receive an ASUS X99 Deluxe engineering sample so Overclockers.ru was kind enough to send us an image of the box art. They claim a 60% improvement in the CPU sector and 12.5% improvement (3000Mhz) for DDR4 RAM. Now there’s something else I noticed here, ASUS’s language is quite loose, these extra six pinouts might just be the six sections where the excess contacts are. Which means that there could be more or less than just six pins. Either way, you know the drill. Whatever the additional pin count is, add that to 2011 and you get the real name of the socket present in these special ASUS mobos.

Source: http://wccftech.com/asus-oc-socket-examined-lga-2011/#ixzz3C0poTe7b

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Intel Readying 15-core Xeon E7 v2

Reports from ISSCC are coming out that Intel is preparing to launch a 15-core Xeon CPU.  The 15-core model was postulated before Ivy Bridge-E launch, along with 12-core and 10-core models – the latter two are currently on the market but Intel was rather silent on the 15-core SKU, presumably because it harder to manufacturer one with the right voltage characteristics.  Releasing a 15-core SKU is a little odd, and one would assume is most likely a 16-core model with one of the cores disabled – based on Intel’s history I doubt this core will be able to be re-enabled should the silicon still work. I just received the official documents and the 15 core SKU is natively 15-core.

Information from the original source on the top end CPU is as follows:

•  4.31 billion transistors
•  Will be in the Xeon E7 line-up, suited for 4P/8P systems (8 * 15 * 2 = 240 threads potential)
•  2.8 GHz Turbo Frequency (though the design will scale to 3.8 GHz)
•  150W TDP
•  40 PCIe lanes

Judging by the available information, it would seem that Intel are preparing a stack of ‘Ivytown’ processors along this design, and thus a range of Xeon E7 processors, from 1.4 GHz to 3.8 GHz, drawing between 40W and 150W, similar to the Xeon E5 v2 range.

Predictions have Ivytown to be announced next week, with these details being part of the ISSCC conference talks.  In comparison to some of the other Xeon CPUs available, as well as the last generation:

Intel Xeon Comparison
	Xeon E3-1280 v3	Xeon E5-2687W	Xeon E5-2697 v2	Xeon E7-8870	Xeon E7-8890 v2
Socket	LGA1150	LGA2011	LGA2011	LGA1567	LGA2011
Architecture	Haswell	Sandy Bridge-EP	Ivy Bridge-EP	Westmere-EX	Ivy Bridge-EX
Codename	Denlow	Romley	Romley	Boxboro	Brickland
Cores / Threads	4 / 8	8 / 16	12 / 24	10 / 20	15 / 30
CPU Speed	3.6 GHz	3.1 GHz	2.7 GHz	2.4 GHz	2.8 GHz
CPU Turbo	4.0 GHz	3.8 GHz	3.5 GHz	2.8 GHz	2.8 GHz
L3 Cache	8 MB	20 MB	30 MB	30 MB	37.5 MB
TDP	82 W	150 W	130 W	130 W	155 W
Memory	DDR3-1600	DDR3-1600	DDR3-1866	DDR3-1600	DDR3-1600
DIMMs per Channel	2	2	2	2	3 ?
Price at Intro	$612	$1885	$2614	$4616	>$5000 ?

According to CPU-World, there are 8 members of the Xeon E7-8xxx v2 range planned, from 6 to 15 cores and 105W to 155W, along with some E7-4xxx v2 also featuring 15 core models, with 2.8 GHz being the top 15-core model speed at 155W. 

All this is tentative until Intel makes a formal announcement, but there is clearly room at the high end.  The tradeoff is always between core density and frequency, with the higher frequency models having lower core counts in order to offset power usage.  If we get more information from ISSCC we will let you know.

Original Source: PCWorld

Update: Now I have time to study the document supplied by Intel for ISSCC, we can confirm the 15-core model with 37.5 MB L3 cache, using 22nm Hi-K metal-gate tri-gate 22nm CMOS with 9 metal layers.  All the Ivytown processors will be harvested from a single die:

Ivytown Die Shot

The design itself is capable of 40W to 150W, with 1.4 GHz to 3.8 GHz speeds capable.  The L3 cache has 15x 2.5MB slices, and data arrays use 0.108µm2 cells with in-line double-error-correction and triple-error-detection (DECTED) with variable latency.  The CPU uses three clock domains as well as five voltage domains:

Level shifters are placed between the voltage domains, and the design uses lower-leakage transistors in non-timing-critical paths, acheving 63% use in the cors and 90% in non-core area.  Overall, leakage is ~22% of the total power.

The CPUs are indeed LGA2011 (the shift from Westmere-EX, skipping over Sandy Bridge, should make it seem more plausible), and come in a 52.5x51.0mm package with four DDR3 channels.  That would make the package 2677 mm2, similar to known Ivy Bridge-E Xeon CPUs.

CPU-World's list of Xeon E7 v2 processors come from, inter alia, this non-Intel document, listing the 105W+ models.

Check out the article over at anandtech.